{"data":{"company":{"name":"Synopsys","slug":"synopsys","logo_url":"https://logos.yubhub.co/careers.synopsys.com.png","canonical_domain":"careers.synopsys.com","editorial":null,"wikidata_id":"Q2303478","founded":"1986-01-01","ceo":"Aart de Geus","founders":["Alberto Sangiovanni-Vincentelli","Aart de Geus"],"hq_location":"Mountain View","industry":"software industry","employee_count":null,"official_website":"https://www.synopsys.com/","wikipedia_url":"https://en.wikipedia.org/wiki/Synopsys","stock_ticker":"SNPS","stock_price":424.24,"market_cap":null,"revenue":null,"ipo_date":"1992-02-26","sector":"Technology","full_time_employees":28000,"company_description":"Synopsys, Inc. provides electronic design automation software products used to design and test integrated circuits. The company offers Fusion Design Platform that provides digital design implementation solutions; Verification Continuum Platform that provides virtual prototyping, static and formal verification, simulation, emulation, field programmable gate array (FPGA)-based prototyping, and debug solutions; and FPGA design products that are programmed to perform specific functions. It also provides intellectual property (IP) solutions for USB, PCI Express, DDR, Ethernet, SATA, MIPI, HDMI, and Bluetooth low energy applications; analog IP, including data converters and audio codecs; and system-on-chip (SoC) infrastructure IP, datapath and building block IP, and verification IP products, as well as mathematical and floating-point components, and Arm AMBA interconnect fabric and peripherals. In addition, the company offers logic libraries and embedded memories; configurable processor cores and application-specific instruction-set processor tools for embedded applications; IP subsystems for audio, sensor, and data fusion functionality; and security IP solutions. Further, it provides Platform Architect solutions for SoC architecture analysis and optimization; virtual prototyping solutions; and HAPS FPGA-based prototyping systems, as well as a series of tools used in the design of optical systems and photonic devices. Additionally, the company offers security testing, managed services, programs and professional services, and training that enable its customers to detect and remediate security vulnerabilities, and defects in the software development lifecycle, as well as manufacturing solutions. It serves electronics, financial services, automotive, medicine, energy, and industrial areas. The company was incorporated in 1986 and is headquartered in Mountain View, California.","twitter_username":"Synopsys","linkedin_id":null,"instagram_username":null,"facebook_id":"Synopsys","parent_org":null,"country":"United States","github_org":null,"github_public_repos":null,"github_followers":null,"github_verified":0,"github_description":null,"github_location":null,"github_blog":null,"github_twitter":null,"stock_exchange":null,"stock_beta":1.156,"stock_range":"365.74-651.73","stock_is_actively_trading":1,"fmp_image":"https://images.financialmodelingprep.com/symbol/SNPS.png","fmp_address":"675 Almanor Avenue","fmp_city":"Sunnyvale","fmp_state":"CA","fmp_country":"US","recent_news":[{"title":"Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows - Synopsys","url":"https://news.google.com/rss/articles/CBMi4AFBVV95cUxNYWZ5dVZyejctdlFMUl9Ca2dwQTBpUXVjY0ZNUWpRZzlrek1fUVREQmpINUF4T05nemE2Snp0cUZUVmRLZnR2eThoV0xQczg0MTZNOWhjN09EUXF5TWlrUmpaalYxM3J1YTkxUkV5NUFtbkJJTkswV1FVT1JZS0w1RHdzUGQ3elpzZTFKdURMSURpam1aai16bm5fS2V2bS1mUHROMjFPM0M3RWluM0VCekR1UEpKR2QyczUxcXNBeFFNOUlpZUxLWkJpVWF3MTFDNXl1ZlAxdHZQOEN1VXVkQg?oc=5","publisher":"Synopsys","date":"2026-04-22","snippet":"Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows Synopsys"},{"title":"Which Is a Better Investment, Cadence Design Systems Inc or Synopsys, Inc. Stock? - AAII","url":"https://news.google.com/rss/articles/CBMixgFBVV95cUxNaUpnU2pibklXaTZrazkwR0p3RWdsNGpPMjBmSE5tRkZvRlVzOWpRMTdoT1VCanozUmVLOUE4TUozUUZ6RWFBZ3Z5VEU2ck9aQTQ4Qms1cUpHekFfOTZKOEstQ1g4Q2RJNko4RXdxNFRweGtBT0txWWRpaHBSYW9ENjdjQnFuSHo5b0tPTXFVYXRXRV9wemNlMzNveVZpWDF4aU1XaC1GQzZMNGNqcnA3cjRrYXpmNHZEWllfS3Z2QmVqNXNMckE?oc=5","publisher":"AAII","date":"2026-05-17","snippet":"Which Is a Better Investment, Cadence Design Systems Inc or Synopsys, Inc. Stock? AAII"},{"title":"Synopsys Stock (SNPS) Opinions on TSMC Partnership - Quiver Quantitative","url":"https://news.google.com/rss/articles/CBMikAFBVV95cUxPLXlnN3poN2NEd1dyemh0Qml6Y28talFlU1NiQjgyenBoZkZSQURONm53VDduRnA4R0pyb0dNMVFEbGROeFRmMGRhdG5zR0EwZjlZUmUteUJycDFEcnpDcUlqZERUSFpfbzZKTFFhR2Y1SzY4NkJLRGtjbDR4NmZ0c19qellEUmRVUmZVYkdGbTI?oc=5","publisher":"Quiver Quantitative","date":"2026-04-25","snippet":"Synopsys Stock (SNPS) Opinions on TSMC Partnership Quiver Quantitative"},{"title":"Atomera Extends Collaboration With Synopsys to Accelerate GaN Modeling in High-Value RF and Power Devices - Business Wire","url":"https://news.google.com/rss/articles/CBMi9AFBVV95cUxNT1dUa21sdkZmcXNJTG14djBZVlNtU1BrV0lxSkRuM3J0RVIwZDZzd0VTWHphMGlhOXJrbVBhMC1WbjNwVXYzN04xcHE1NDRvckV0dEVpb2tJSnp0TDVMaGs2djU2N2RoZUtYaFlXQkt4ajJ0bEJqZWhrZXpUMjl6dDJ2X0h3LVVvYjB6enFUclotRjJuRTMxTWVoNmtwUEExV1NnQW82Sm9OZ2dtaEhFRlNDMDA5ZjJ5ZlEwZ21hYkhVUUg1OGRoYVlnZzdwYnFyWWFZREhHLWQ0T0U0anBkNW94Y05CXzJWa2VHUTQ5RUpZV1NY?oc=5","publisher":"Business Wire","date":"2026-04-23","snippet":"Atomera Extends Collaboration With Synopsys to Accelerate GaN Modeling in High-Value RF and Power Devices Business Wire"},{"title":"Quantinuum Announces Collaboration with Synopsys Toward Advancing Industrial Design with Quantum Computing - Quantinuum","url":"https://news.google.com/rss/articles/CBMi4gFBVV95cUxONlVrVTJzVjkzUXdqUnlzSzNzd0NMNUlXMy1uTkhkMWVtcVprRWF0SmxGYU9IcFBaWXYyVERVczRtU000bXBDQkpMZVBxZXJ3cFJQZGVJOEdRZy1velUzbVNzZ3hXaVNPQjNIZmhPcExpMTVEYjl1SzVjZWY4cmhwWlF0UTNlMWQzYVlKUVNaMHljZDBCS3dpTk02TkQ2UXVsd1RtTzh6b25aaUprRk1QM2dVejJXVHZjTHdNTzBUZWNrUmwteW9NaUNDZC0tSzAxbkw1b2F0X1ZueDFoRV9JOFBn?oc=5","publisher":"Quantinuum","date":"2026-05-19","snippet":"Quantinuum Announces Collaboration with Synopsys Toward Advancing Industrial Design with Quantum Computing Quantinuum"}],"search_interest_index":25,"search_interest_trend":"stable","wikipedia_monthly_views":16214,"hn_mention_count":null,"hn_top_stories":[],"wayback_first_year":null,"sec_incorporation_state":null,"sec_latest_filing_type":null,"sec_latest_filing_date":null,"sec_filings":[],"research_papers_count":null,"research_citations_count":null,"research_h_index":null,"research_topics":[],"is_federal_contractor":null,"earnings_calendar":[],"industry_canonical":null,"enrichment_sources":["wikidata","fmp","news"],"last_enriched_at":"2026-03-20T16:27:00.861Z"},"hiring":{"total_jobs":634,"categories":[{"category":"engineering","count":562},{"category":"sales","count":33},{"category":"finance","count":9},{"category":"marketing","count":8},{"category":"product management","count":4},{"category":"operations","count":3},{"category":"general management","count":3},{"category":"strategic planning and corp dev","count":2},{"category":"legal","count":2},{"category":"hr","count":2},{"category":"sales enablement","count":1},{"category":"people","count":1},{"category":"manufacturing","count":1},{"category":"it","count":1},{"category":"information technology","count":1},{"category":"business development","count":1}],"experience_levels":[{"level":"senior","count":387},{"level":"staff","count":178},{"level":"mid","count":35},{"level":"entry","count":13},{"level":"executive","count":10}],"work_arrangements":[{"arrangement":"onsite","count":487},{"arrangement":"remote","count":55},{"arrangement":"hybrid","count":11}],"top_titles":[{"title":"Applications Engineering, Staff Engineer","count":12},{"title":"Analog Design, Staff Engineer","count":11},{"title":"Layout Design, Staff Engineer","count":10},{"title":"R&D Engineering, Staff Engineer","count":8},{"title":"ASIC Physical Design, Staff Engineer","count":6},{"title":"ASIC Digital Design, Staff Engineer","count":6},{"title":"ASIC Digital Design, Sr Staff Engineer","count":6},{"title":"Applications Engineering, Sr Staff Engineer","count":6},{"title":"Applications Engineering, Principal Engineer","count":5},{"title":"SOC Engineering, Sr Staff Engineer","count":4},{"title":"Sales Account Management, Staff","count":4},{"title":"R&D Engineering, Engineer","count":4},{"title":"Layout Design, Sr Engineer","count":4},{"title":"Staff Engineer (R&D Engineering)","count":3},{"title":"Staff Application Engineer – Physical Implementation","count":3}],"locations":[{"location":"bengaluru","count":103},{"location":"sunnyvale","count":39},{"location":"noida","count":24},{"location":"hyderabad","count":22},{"location":"mississauga","count":21},{"location":"ho chi minh city","count":18},{"location":"hsinchu","count":17},{"location":"yerevan","count":16},{"location":"united states","count":16},{"location":"bengaluru, karnataka","count":14}],"skills":[{"skill":"Python","required":167,"preferred":18,"total":185},{"skill":"Tcl","required":107,"preferred":16,"total":123},{"skill":"Perl","required":94,"preferred":15,"total":109},{"skill":"EDA Tools","required":51,"preferred":5,"total":56},{"skill":"Verilog","required":49,"preferred":2,"total":51},{"skill":"C++","required":47,"preferred":3,"total":50},{"skill":"SystemVerilog","required":43,"preferred":3,"total":46},{"skill":"Synthesis","required":41,"preferred":1,"total":42},{"skill":"UVM","required":40,"preferred":1,"total":41},{"skill":"C/c++","required":38,"preferred":3,"total":41},{"skill":"PCIe","required":31,"preferred":5,"total":36},{"skill":"DDR","required":26,"preferred":8,"total":34},{"skill":"Data Structures","required":30,"preferred":1,"total":31},{"skill":"RTL Design","required":28,"preferred":0,"total":28},{"skill":"Algorithms","required":26,"preferred":2,"total":28},{"skill":"Scripting Languages","required":23,"preferred":5,"total":28},{"skill":"Fusion Compiler","required":25,"preferred":3,"total":28},{"skill":"Ethernet","required":24,"preferred":4,"total":28},{"skill":"Verification","required":24,"preferred":3,"total":27},{"skill":"System Verilog","required":27,"preferred":0,"total":27}],"salary_stats":{"count":173,"min":84000,"q1":140000,"median":180000,"q3":217500,"max":335000},"job_types":[{"type":"full-time","count":539},{"type":"employee","count":88},{"type":"internship","count":7}],"latest_jobs":[{"id":"job_e028d778-231","title":"Digital Verification, Principal Engineer - 15149 HPC IP","source_url":"https://careers.synopsys.com/job/austin/digital-verification-principal-engineer-15149-hpc-ip/44408/95396146496","location":"Austin, Texas","job_type":"Employee","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are an experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.</p>\n<h4>Responsibilities</h4>\n<ul>\n<li>Designing and implementing verification environments to ensure the correctness of Interface IP protocols.</li>\n<li>Creating and executing detailed test plans to verify complex ASIC designs.</li>\n<li>Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.</li>\n<li>Collaborating with design and architecture teams to identify and fix bugs.</li>\n<li>Performing functional coverage analysis and driving coverage closure.</li>\n<li>Mentoring and guiding junior verification engineers in best practices and methodologies.</li>\n</ul>\n<h4>The Impact You Will Have</h4>\n<ul>\n<li>Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.</li>\n<li>Enhancing the robustness and efficiency of our verification processes and methodologies.</li>\n<li>Contributing to the successful launch of Interface IP products, impacting various industries.</li>\n<li>Driving innovation and excellence within the verification team.</li>\n<li>Improving the overall performance and functionality of Synopsys&#39; IP offerings.</li>\n<li>Fostering a culture of continuous improvement and technical excellence.</li>\n</ul>\n<h4>Requirements</h4>\n<ul>\n<li>Extensive experience in ASIC digital verification, specifically with UAL, Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.</li>\n<li>Proficiency in SystemVerilog and UVM methodologies.</li>\n<li>Strong understanding of digital design and verification concepts.</li>\n<li>Experience with simulation tools such as VCS, ModelSim, or similar.</li>\n<li>Excellent problem-solving skills and attention to detail.</li>\n</ul>\n<h4>Who You Are</h4>\n<ul>\n<li>Detail-oriented with a strong analytical mindset.</li>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n<li>Collaborative team player who thrives in a dynamic environment.</li>\n<li>Proactive and self-motivated, with a commitment to continuous learning.</li>\n<li>Mentor and leader, capable of guiding and developing junior engineers.</li>\n</ul>\n<h4>Benefits</h4>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>","enriched_at":1781904407868},{"id":"job_ee5a5e96-b71","title":"Senior Technical Account Manager (High-Tech)","source_url":"https://careers.synopsys.com/job/seoul/senior-technical-account-manager-high-tech/44408/96637227984","location":"Seoul","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>You are a skilled professional with an engineering background and a passion for building strong customer relationships to deliver technical solutions that drive business outcomes. Adept at bridging technical and business conversations, you excel in fast-paced environments and enjoy collaborating with diverse teams.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Establish long-term sustainable relationships with key customers, aligning Synopsys simulation and analysis solutions with client business initiatives</li>\n<li>Collaborate with the Account Management Team to identify, define, and execute strategic technical engagements</li>\n<li>Manage a large range of worldwide resources to deliver customer success</li>\n<li>Ensure customer needs are mapped to business impact and communicated effectively with stakeholders</li>\n<li>Coordinate with account-based marketing to drive technology proliferation campaigns</li>\n<li>Participate in field-factory interlock on Synopsys S&amp;A product enhancement and competitive solution positioning</li>\n<li>Define and drive technical campaigns for complex engagements and advise on industry-related trends</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate customer success and satisfaction by enabling innovative applications of Synopsys technology</li>\n<li>Strengthen customer relationships and drive long-term business growth through technical excellence and trusted advisory</li>\n<li>Influence product strategy and roadmap by providing direct feedback from the field</li>\n<li>Enhance the team&#39;s knowledge base by sharing insights and best practices from customer engagements</li>\n<li>Reduce time-to-value for customers adopting new solutions, improving retention and expansion rates</li>\n<li>Position Synopsys as a preferred partner in the electronics, high-tech, and semiconductor industries</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BS or MS or PhD in Electronics, Thermal, Mechanical engineering or related field</li>\n<li>Minimum 4 years in customer-facing technical role such as application engineering, technical support, or consulting services leveraging simulation software</li>\n<li>Demonstrated understanding of Synopsys S&amp;A solutions and ability to communicate technical engagements and business impact</li>\n<li>Strong proficiency with Synopsys simulation and analysis (S&amp;A) tools and workflows in electromagnetic, signal integrity, or semiconductor-related areas is preferred</li>\n<li>Previous experience working in Electronics, particularly in high-frequency or semiconductor domains is preferred</li>\n</ul>\n<p><strong>Benefits:</strong></p>\n<ul>\n<li>Comprehensive range of health, wellness, and financial benefits</li>\n</ul>","enriched_at":1781902558392},{"id":"job_4ce3dcef-366","title":"Senior Applications Engineer","source_url":"https://careers.synopsys.com/job/vancouver/senior-applications-engineer/44408/96623912960","location":"Vancouver, BC","job_type":"full-time","experience_level":"senior","work_arrangement":"remote","category":"Engineering","description":"<p>We are looking for a Senior Applications Engineer to support tier-one accounts on problems that directly affect tape-out schedules, working with a global team that values technical rigor and customer impact.</p>\n<p>You will bring practical experience in semiconductor design with a strong foundation in power integrity, thermal integrity, or timing signoff. You have worked with tools like RedHawk-SC, PrimeTime, or Totem in production environments and understand what it takes to move a chip through signoff successfully.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Supporting key accounts on power integrity, thermal integrity, and signal integrity signoff</li>\n<li>Meeting with customers multiple times a day to understand technical requirements, debug complex design issues, and deliver solutions that accelerate their tape-out schedules</li>\n<li>Translating customer needs into clear technical requirements for internal R&amp;D teams, writing specs that bridge the gap between electrical engineering and software development</li>\n<li>Working on 3D-IC power, multiphysics and thermal integrity signoff</li>\n<li>Deploying and validating new workflows and integrated capabilities in live customer environments</li>\n<li>Supporting both post-sales deployments and pre-sales engagements</li>\n<li>Building internal expertise on classic Synopsys tools and workflows</li>\n<li>Working with global engineering teams to align customer feedback with product roadmaps</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Driving adoption of Synopsys and Ansys signoff tools at tier-one accounts</li>\n<li>Helping customers resolve complex power, thermal, timing, and reliability challenges</li>\n<li>Influencing the evolution of industry-leading EDA products</li>\n<li>Strengthening customer relationships by acting as a trusted technical advisor</li>\n<li>Improving internal capability through knowledge sharing and cross-training</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering with at least 2 years of experience, or Master&#39;s degree in Electrical Engineering with at least 1 year of experience</li>\n<li>At least 1 year of hands-on experience in semiconductor design with strong expertise in PDN/EMIR, static timing analysis, timing closure, thermal integrity, or ECO flows</li>\n<li>Hands-on experience with tools such as RedHawk-SC, RedHawk-SC ElectroThermal, Totem, Totem-SC, PrimeTime, or PrimeClosure</li>\n<li>Strong understanding of signoff flows including power integrity, thermal integrity, timing analysis, and reliability</li>\n<li>Ability to debug and solve complex design issues independently</li>\n<li>Programming or scripting skills in Python, TCL, or similar languages</li>\n</ul>","enriched_at":1781902525039},{"id":"job_20c3a44a-98d","title":"Applications Engineering, Engineer","source_url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-engineer/44408/96637227952","location":"Bengaluru, Karnataka","job_type":"full-time","experience_level":"entry","work_arrangement":null,"category":"Engineering","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You are an early-career engineer passionate about solving challenging design problems in the semiconductor industry. With a strong foundation in physical implementation flows and a customer-first mindset, you’re excited to learn and contribute on advanced technology nodes using Synopsys’ industry-leading EDA tools.</p>\n<h3>Responsibilities</h3>\n<ul>\n<li>Solve complex PPA (Performance, Power, Area) challenges using Synopsys’ latest implementation technologies, including AI/ML Implementation, Physical Synthesis RTL-GDS.</li>\n<li>Solve complex Formal verification challenges, early power estimation using latest technologies.</li>\n<li>Benchmark Synopsys solutions against competitors to displace alternative implementation flows and demonstrate superior results.</li>\n<li>Develop, debug, and optimize Synthesis implementation methodologies and flows for emerging semiconductor technologies.</li>\n<li>Provide technical solutions by identifying design and EDA tool issues and delivering actionable resolutions for customers.</li>\n<li>Translate technical findings into requirements for R&amp;D, driving tool enhancements and adaptive long-term solutions.</li>\n<li>Deploy new technology features in the latest EDA tool versions and enable customer migration for best-in-class PPA.</li>\n<li>Collaborate closely with Synopsys R&amp;D and product development teams to shape future technology directions.</li>\n</ul>\n<h3>The Impact You Will Have</h3>\n<ul>\n<li>Elevate customer success by delivering robust technical solutions and enabling optimal tool utilization.</li>\n<li>Drive Synopsys’ competitive advantage by displacing rival implementation flows and showcasing superior PPA outcomes.</li>\n<li>Contribute to the enhancement of Synopsys products by providing critical feedback and requirements to R&amp;D.</li>\n<li>Accelerate customer adoption of new technology nodes and EDA tool versions to achieve best-in-class results.</li>\n<li>Strengthen Synopsys’ reputation as the industry leader in physical implementation and innovation.</li>\n<li>Foster long-term customer relationships through proactive engagement and continuous support.</li>\n</ul>\n<h3>Requirements</h3>\n<ul>\n<li>B.Tech or M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related fields from a recognized institution.</li>\n<li>0-2 years of experience in synthesis, physical design, or ASIC implementation, whether from internships, academic projects, or early-career roles.</li>\n<li>Familiar with methodology changes aimed at achieving targeted PPA metrics for complex designs.</li>\n<li>Proficiency in synthesis and formal verification tools and flows is highly advantageous.</li>\n<li>Knowledge in scripting skills (TCL, Unix, Perl) for automation and debugging.</li>\n<li>Excellent communication skills, including the ability to interface effectively with customers and internal teams.</li>\n</ul>\n<h3>Benefits</h3>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>","enriched_at":1781902498097},{"id":"job_b9524be1-e1f","title":"Scientist- ASIC Verification, Interface IP- PCIe/CXL","source_url":"https://careers.synopsys.com/job/bengaluru/scientist-asic-verification-interface-ip-pcie-cxl/44408/96653311680","location":"Bengaluru, Karnataka","job_type":"full-time","experience_level":"senior","work_arrangement":"onsite","category":"Engineering","description":"<p>You are a seasoned verification expert with over a decade of experience in building verification environments for complex digital designs.</p>\n<p>As a Scientist- ASIC Verification, Interface IP- PCIe/CXL at Synopsys, you will define and architect RTL verification strategies for Synopsys Interface IP controllers, focusing on PCIe, CXL, and UCIe protocols.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Building and owning testbench architectures using UVM and advanced verification methodologies</li>\n<li>Developing comprehensive verification plans that map protocol specifications to coverage models and corner cases</li>\n<li>Debugging complex protocol interactions and mentoring verification engineers across the team</li>\n</ul>\n<p>The ideal candidate will have 20+ years of hands-on experience in ASIC RTL verification, deep expertise in PCIe, CXL, or UCIe protocol verification, and a proven ability to define and execute testbench architecture using SystemVerilog, UVM, and constrained-random verification techniques.</p>\n<p>In return, Synopsys offers a comprehensive range of health, wellness, and financial benefits, including competitive salaries, medical and healthcare plans, time away, family support, and retirement plans.</p>","enriched_at":1781902496976},{"id":"job_d5c316f8-204","title":"Digital Design Architect - 15036 HPC IP","source_url":"https://careers.synopsys.com/job/austin/digital-design-architect-15036-hpc-ip/44408/91458064976","location":"Austin, Texas","job_type":"full-time","experience_level":"senior","work_arrangement":"onsite","category":"Engineering","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are an experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. 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