{"data":{"company":{"name":"Synopsys","slug":"synopsys","logo_url":"https://logos.yubhub.co/careers.synopsys.com.png","canonical_domain":"careers.synopsys.com","editorial":null,"wikidata_id":"Q2303478","founded":"1986-01-01","ceo":"Aart de Geus","founders":["Alberto Sangiovanni-Vincentelli","Aart de Geus"],"hq_location":"Mountain View","industry":"software industry","employee_count":null,"official_website":"https://www.synopsys.com/","wikipedia_url":"https://en.wikipedia.org/wiki/Synopsys","stock_ticker":"SNPS","stock_price":424.24,"market_cap":null,"revenue":null,"ipo_date":"1992-02-26","sector":"Technology","full_time_employees":28000,"company_description":"Synopsys, Inc. provides electronic design automation software products used to design and test integrated circuits. The company offers Fusion Design Platform that provides digital design implementation solutions; Verification Continuum Platform that provides virtual prototyping, static and formal verification, simulation, emulation, field programmable gate array (FPGA)-based prototyping, and debug solutions; and FPGA design products that are programmed to perform specific functions. It also provides intellectual property (IP) solutions for USB, PCI Express, DDR, Ethernet, SATA, MIPI, HDMI, and Bluetooth low energy applications; analog IP, including data converters and audio codecs; and system-on-chip (SoC) infrastructure IP, datapath and building block IP, and verification IP products, as well as mathematical and floating-point components, and Arm AMBA interconnect fabric and peripherals. In addition, the company offers logic libraries and embedded memories; configurable processor cores and application-specific instruction-set processor tools for embedded applications; IP subsystems for audio, sensor, and data fusion functionality; and security IP solutions. Further, it provides Platform Architect solutions for SoC architecture analysis and optimization; virtual prototyping solutions; and HAPS FPGA-based prototyping systems, as well as a series of tools used in the design of optical systems and photonic devices. Additionally, the company offers security testing, managed services, programs and professional services, and training that enable its customers to detect and remediate security vulnerabilities, and defects in the software development lifecycle, as well as manufacturing solutions. It serves electronics, financial services, automotive, medicine, energy, and industrial areas. The company was incorporated in 1986 and is headquartered in Mountain View, California.","twitter_username":"Synopsys","linkedin_id":null,"instagram_username":null,"facebook_id":"Synopsys","parent_org":null,"country":"United States","github_org":null,"github_public_repos":null,"github_followers":null,"github_verified":0,"github_description":null,"github_location":null,"github_blog":null,"github_twitter":null,"stock_exchange":null,"stock_beta":1.156,"stock_range":"365.74-651.73","stock_is_actively_trading":1,"fmp_image":"https://images.financialmodelingprep.com/symbol/SNPS.png","fmp_address":"675 Almanor Avenue","fmp_city":"Sunnyvale","fmp_state":"CA","fmp_country":"US","recent_news":[{"title":"Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology - Synopsys","url":"https://news.google.com/rss/articles/CBMi8gFBVV95cUxQeTdfZzAwNlFHX2RGRDhJTFRsaW1QTTdyTzRDejNJSm9COFF0XzhuS0RrYXRoYkxYc184Yk16VnBBLUFGRXR4TlFjN2lqNVhWVG1tM2pSQ1pXU2dRWXhCSVEzUjFhaFJZcjFOekVsUmRkaUl3X0ZsVGZ1WlRxZFdvX0ZfQlBNcVZ6UUVmMDBWSU96OGRTSFVpYnRTZmpXZEdtSmNfUlpBUDFQaEcyaWFQNmhhNkFseGw0WC1ON0w2aUlOZDhJTmFGc0FRUmYwMm1qRmNDOUxpQXRGNGNsWE1LQk8zTmF0c2ZLQXdCX3NyYkxzUQ?oc=5","publisher":"Synopsys","date":"2026-07-27","snippet":"Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology Synopsys"},{"title":"Synopsys to cut chip fab manufacturing control software in shift to AI design, sources say - Reuters","url":"https://news.google.com/rss/articles/CBMi0AFBVV95cUxQb3ZSZFk2bGd3VnR4MjRhQWxsa0RkS29maW1PSFNwblpzd2o5Sm1qRVMxTmRfbEF2ZWJoSUh6WE5mM3ZYTnJ1NEp3LTJ3MnBaU2FzaTlUcF9hOFhrUlhyZ0I3dDc3N0EzeUhvRVJCMnJicU44NWVVbVFYSWRCV29hWTIwZERWRGlYT2hlQ3FzVVpZaHR3UG4zR1V2VGYzQzAwM2tFbHRUV2lxUTk0M0hjOWo3bGZFZnE1YlJ1N1BUQ0ZIS3JCTHpDT2p0TW5sMkhO?oc=5","publisher":"Reuters","date":"2026-07-06","snippet":"Synopsys to cut chip fab manufacturing control software in shift to AI design, sources say Reuters"},{"title":"Synopsys (SNPS) Dips More Than Broader Market: What You Should Know - Yahoo Finance","url":"https://news.google.com/rss/articles/CBMinAFBVV95cUxPTFJycVpoSUJtbXFXejZ4MWd0aFJfaUoyTGtEbmpFaGNfdXZaTHhzSHFldHdIOF9hTFpGRjc4Z21nUUhHaXEtVlpMb2lEM2tuTE1Cd2o0VmRzTllYblpHSkFZQVF2ZUdUSVcyS3RibERHMGJWSGxPcEQ4ZU1NNnUyMzhpZXBOUndaZVBad2N1UGdVZkpqY3pTQTZHMlQ?oc=5","publisher":"Yahoo Finance","date":"2026-07-16","snippet":"Synopsys (SNPS) Dips More Than Broader Market: What You Should Know Yahoo Finance"},{"title":"Synopsys Finds No Evidence of Data Breach Amid Bosch Hack Claims - SecurityWeek","url":"https://news.google.com/rss/articles/CBMioAFBVV95cUxNVDR4a3JoYlNTS01kZ2Zlek43dW9hM05wUzRBVzB5RFFhdmx3OVU3dmJmYWVpamh2ZjlxMF9yT3laX1ZiMU1PMlNWN1V0WHFCMnJ6bTlpRGxiNmsyY2J0Q2FUamRNejJUa1lfYnFBbWptNzNjNUlLQ21DWjE2dEdIeDFfN0RHT1BPUWdjVG9hZU1yMmNoa1FBTlo2SzVGZUpk0gGmAUFVX3lxTE91OTVuMWZOUGt0dlpUV09QcmRDOXJ6ZS1feEhacTNMUF9vZEE5TVZObGkydGtvTjM5RHYzOFp2Q2NpWkFMVTdneVBKMklsSFk0d0F6Qm01MGdRSTQyOVlBcGFxV2h6ZVRBcU9pUE5zMnNUY1ZQNFhocUpYaWd6bm00andqMlhHWXBoN1JCc1A3b2JURnNFaWxVZFdCVFdySzdtdEVEdUE?oc=5","publisher":"SecurityWeek","date":"2026-07-14","snippet":"Synopsys Finds No Evidence of Data Breach Amid Bosch Hack Claims SecurityWeek"},{"title":"Synopsys Advances Agentic AI Chip Design with AMD and Microsoft - PR Newswire","url":"https://news.google.com/rss/articles/CBMiuwFBVV95cUxQS09nVE9ab0hoX0IwWVlUNV9Rdjk1b0QwWTFVZG54MDljQTNrWG4tOVhta1lOekRuQktzOFlmbTAtcDQxNmE3VWpMbXhYbEVvQkhINlR1RUFycnNqVFNkOFJCVFRYQVFhVU9GemxsSXJUV3E0QmRkNGtsS0YwZXFRVG1YdklrNS16TUJWenBuc1R0ZFJ6dmpTQmhYU1lwQUtQaFJBbmVFV2c1My1oeFlOMkJUemdhR3g5RVpN?oc=5","publisher":"PR Newswire","date":"2026-07-27","snippet":"Synopsys Advances Agentic AI Chip Design with AMD and Microsoft PR Newswire"}],"search_interest_index":25,"search_interest_trend":"stable","wikipedia_monthly_views":16214,"hn_mention_count":null,"hn_top_stories":[],"wayback_first_year":null,"sec_incorporation_state":null,"sec_latest_filing_type":null,"sec_latest_filing_date":null,"sec_filings":[],"research_papers_count":null,"research_citations_count":null,"research_h_index":null,"research_topics":[],"is_federal_contractor":null,"earnings_calendar":[],"industry_canonical":null,"enrichment_sources":["wikidata","fmp","news"],"last_enriched_at":"2026-03-20T16:27:00.861Z"},"hiring":{"total_jobs":275,"categories":[{"category":"engineering","count":237},{"category":"product management","count":10},{"category":"finance","count":6},{"category":"it","count":5},{"category":"sales","count":4},{"category":"operations","count":3},{"category":"marketing","count":2},{"category":"legal","count":2},{"category":"strategic planning and corp dev","count":1},{"category":"manufacturing","count":1},{"category":"information technology","count":1},{"category":"hr","count":1},{"category":"general management","count":1},{"category":"data science","count":1}],"experience_levels":[{"level":"senior","count":193},{"level":"staff","count":62},{"level":"mid","count":8},{"level":"executive","count":8},{"level":"entry","count":2}],"work_arrangements":[{"arrangement":"onsite","count":167},{"arrangement":"remote","count":28},{"arrangement":"hybrid","count":9}],"top_titles":[{"title":"R&D Engineering, Staff Engineer","count":7},{"title":"Applications Engineering, Staff Engineer","count":7},{"title":"Applications Engineering, Sr Staff Engineer","count":4},{"title":"Analog Design, Sr Staff Engineer","count":4},{"title":"Principal SerDes Systems Engineer","count":3},{"title":"Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification","count":3},{"title":"ASIC Digital Design, Sr Staff Engineer","count":3},{"title":"ASIC Digital Design, Principal Engineer","count":3},{"title":"Staff Software Engineer","count":2},{"title":"Staff Application Engineer – Physical Implementation","count":2},{"title":"SoC Verification Technical Lead","count":2},{"title":"Soc Engineer (Physical Design)","count":2},{"title":"Senior Staff RTL Design Engineer","count":2},{"title":"Senior R&D Engineer","count":2},{"title":"Project Engineering Management, Sr Staff Engineer","count":2}],"locations":[{"location":"bengaluru","count":32},{"location":"bengaluru, karnataka","count":17},{"location":"sunnyvale, california","count":16},{"location":"sunnyvale","count":13},{"location":"noida, uttar pradesh","count":11},{"location":"hsinchu, taiwan","count":8},{"location":"noida","count":7},{"location":"ho chi minh city","count":7},{"location":"nepean","count":6},{"location":"dublin, leinster","count":6}],"skills":[{"skill":"Python","required":58,"preferred":6,"total":64},{"skill":"Tcl","required":35,"preferred":6,"total":41},{"skill":"Perl","required":33,"preferred":5,"total":38},{"skill":"PCIe","required":21,"preferred":8,"total":29},{"skill":"Verification","required":22,"preferred":2,"total":24},{"skill":"DDR","required":17,"preferred":5,"total":22},{"skill":"Synthesis","required":21,"preferred":0,"total":21},{"skill":"EDA Tools","required":20,"preferred":1,"total":21},{"skill":"Ethernet","required":17,"preferred":1,"total":18},{"skill":"SystemVerilog","required":15,"preferred":0,"total":15},{"skill":"C++","required":15,"preferred":0,"total":15},{"skill":"RTL Design","required":15,"preferred":0,"total":15},{"skill":"Static Timing Analysis","required":15,"preferred":0,"total":15},{"skill":"ASIC Design","required":14,"preferred":1,"total":15},{"skill":"USB","required":10,"preferred":5,"total":15},{"skill":"UVM","required":13,"preferred":1,"total":14},{"skill":"Physical Verification","required":13,"preferred":1,"total":14},{"skill":"Physical Design","required":12,"preferred":1,"total":13},{"skill":"C/c++","required":13,"preferred":0,"total":13},{"skill":"Verilog","required":12,"preferred":1,"total":13}],"salary_stats":{"count":85,"min":64000,"q1":140000,"median":189000,"q3":230000,"max":335000},"job_types":[{"type":"full-time","count":247},{"type":"employee","count":28}],"latest_jobs":[{"id":"job_91dad886-5fc","title":"Physical Design Engineer (Senior/Staff) in District 7","source_url":"https://careers.synopsys.com/job/ho-chi-minh-city/physical-design-engineer-senior-staff-in-district-7/44408/98736242784","location":"Ho Chi Minh City","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years in physical design where routing decisions determine whether a chip tapes out clean or burns weeks in ECO. You know Fusion Compiler or ICC2 from debugging congestion hotspots and timing violations at 2am, not from training slides. P&amp;R is equal parts science and pattern recognition, and you have developed both.</p>\n<p>You do not wait for a perfect floorplan. You flag what will break and propose something workable before it becomes a schedule problem. When extraction results look wrong, you dig until you understand why. The best solutions often come from walking to the frontend team and asking the right question.</p>\n<p>Mentorship matters to you. You remember staring at a million DRC violations as a junior engineer, so you take time to show someone how to read a timing report or why their power grid will not close. You script your way out of repetitive work in TCL or PERL, and you know when automation helps versus when manual is faster.</p>\n<p>At Synopsys, you will work on real SOC designs using the tools the industry depends on. The problems are hard, the work is real, and what you build will matter.</p>\n<h4>What You&#39;ll Be Doing</h4>\n<ul>\n<li>Own physical implementation using Fusion Compiler or ICC2, from floorplanning through routing and signoff closure</li>\n<li>Debug complex P&amp;R issues including timing, congestion, IR drop, and physical verification failures across hierarchical designs</li>\n<li>Guide customer design and CAD teams on tool usage, methodology, and design closure as a trusted technical advisor</li>\n<li>Develop physical design flows and automation scripts in TCL, PERL, or Python to improve efficiency</li>\n<li>Work with Synopsys BU and Sales teams to deploy tool and IP solutions that solve real customer problems</li>\n<li>Mentor junior engineers on P&amp;R fundamentals, debugging techniques, and tool best practices</li>\n</ul>\n<h4>The Impact You Will Have</h4>\n<ul>\n<li>Accelerate customer tapeout schedules by solving physical design bottlenecks that would otherwise cause weeks of delay</li>\n<li>Improve Synopsys physical design methodologies through real-world deployment and customer feedback</li>\n<li>Enable successful Fusion Compiler and ICC2 adoption across customer teams, directly influencing tool ROI</li>\n<li>Reduce design respins by catching physical implementation problems early in the flow</li>\n<li>Build long-term team capability by elevating junior engineer skills and reducing external support dependency</li>\n<li>Shape EDA tool development by surfacing customer pain points that matter</li>\n<li>Contribute to silicon products powering AI, automotive, mobile, and data center applications worldwide</li>\n</ul>\n<h4>What You&#39;ll Need</h4>\n<ul>\n<li>Bachelor&#39;s, Master&#39;s, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or equivalent</li>\n<li>3 to 6+ years hands-on Place and Route experience using Fusion Compiler or ICC2 on complex SOC or ASIC designs</li>\n<li>Strong knowledge of P&amp;R, extraction, static timing analysis, IR drop, and physical verification fundamentals</li>\n<li>Proficiency in TCL, PERL, or Python scripting for automation and flow development</li>\n<li>Solid debugging skills to trace root causes across timing, power, signal integrity, and DRC/LVS domains</li>\n<li>Experience with signoff tools like PrimeTime, Redhawk, StarRC, or ICV is a plus</li>\n<li>Effective English communication skills for customer-facing and cross-functional work</li>\n</ul>","enriched_at":1785878946883},{"id":"job_59010952-377","title":"Network Security Engineer","source_url":"https://careers.synopsys.com/job/porto-salvo/network-security-engineer/44408/98728712240","location":"Porto Salvo, Lisbon District","job_type":"full-time","experience_level":"senior","work_arrangement":"onsite","category":"IT","description":"<p>We are seeking a Network Security Engineer to join our team in Porto Salvo, Lisbon District, Portugal.</p>\n<p>You will be responsible for designing, configuring, deploying, monitoring, and troubleshooting production network infrastructure and associated services. You will also implement network security standards and access controls following NIST frameworks, develop and implement network security policies and procedures, and utilize automation tools and scripts to standardize deployment configurations and environments.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Designing, configuring, deploying, monitoring, and troubleshooting production network infrastructure and associated services</li>\n<li>Implementing network security standards and access controls following NIST frameworks</li>\n<li>Developing and implementing network security policies and procedures</li>\n<li>Implementing and supporting campus and data center macro and micro-segmentation policies</li>\n<li>Utilizing automation tools and scripts to standardize deployment configurations and environments</li>\n<li>Monitoring and analyzing networks for potential security threats and vulnerabilities</li>\n<li>Managing network security infrastructure including SASE, firewalls, VPNs, and ZTA solutions</li>\n<li>Helping maintain and advance Zero Trust Architecture adoption</li>\n<li>Developing and enforcing best practice security standards, compliance, and governance</li>\n<li>Conducting external and internal security audits and assessments to identify potential risks and vulnerabilities in the network infrastructure adhering to industry-standard cybersecurity frameworks</li>\n<li>Staying up to date on emerging network security threats and proof of concepts</li>\n<li>Creating and maintaining documentation of network security designs, processes, and procedures</li>\n<li>Identifying and solving problems related to overall security infrastructure performance, efficiency, and availability in a timely manner</li>\n<li>Contributing to network and security support ticketing and providing timely resolution for end-user issues</li>\n</ul>\n<p>You will have the opportunity to:</p>\n<ul>\n<li>Improve reliability and speed of security operations through automation and AI tools</li>\n<li>Enhance Synopsys&#39; network security posture through the implementation of new vendor solutions</li>\n<li>Ensure compliance with network security standards, governance, and industry best practices</li>\n<li>Provide critical support for global remote field offices and data centers, ensuring secure and reliable network connectivity</li>\n<li>Utilize automation to streamline deployment configurations, improving efficiency and consistency</li>\n<li>Support the advancement and maintenance of Zero Trust Architecture, reinforcing Synopsys&#39; security framework</li>\n<li>Contribute to the resolution of network security issues, minimizing downtime and ensuring business continuity</li>\n</ul>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>4+ years of experience working on current bleeding-edge technology Gartner leaders</li>\n<li>Bachelor&#39;s degree or equivalent work experience</li>\n<li>Proficiency in network configuration management and automation tools (Python, Ansible)</li>\n<li>Familiarity with Rest API automation and configuration management secure coding</li>\n<li>General knowledge of NIST, CIS Benchmark, and/or STIG security frameworks</li>\n<li>Experience with MFA, SSO, SAML deployment</li>\n<li>Familiarity with Clearpass NAC</li>\n<li>Deep understanding of network security systems and protocols such as IPSec, IKE, GRE, TACACS, RADIUS, 802.1x, OSPF, DMVPN, BGP, SD-WAN</li>\n<li>Experience with configuring and troubleshooting Cisco, Versa, and Aruba devices</li>\n<li>Experience with configuring Palo Alto, Zscaler, and SASE solutions</li>\n<li>General knowledge of Frontier AI threat risk and prevention</li>\n<li>Ability to work after hours to support projects and maintenance activities</li>\n<li>Some knowledge of automation and scripting tools such as Python and Ansible</li>\n<li>Ability to create best-practice secure environment diagrams and documentation</li>\n<li>Ability to quickly learn new or unfamiliar technology and products using documentation and internet resources</li>\n<li>Strong verbal, written interpersonal, and communication skills</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>","enriched_at":1785878795930},{"id":"job_3f0be688-f55","title":"Senior R&D Engineer","source_url":"https://careers.synopsys.com/job/canonsburg/senior-r-and-d-engineer/44408/98682479712","location":"Canonsburg, Pennsylvania","job_type":"full-time","experience_level":"senior","work_arrangement":"hybrid","category":"Engineering","description":"<p>We are seeking a Senior R&amp;D Engineer to work in Canonsburg, PA. As a Senior R&amp;D Engineer at Synopsys, you will play a critical role in developing software products and supporting systems for the Electronic Design Automation (EDA) industry.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop software products and supporting systems</li>\n<li>Use advanced technical and problem-solving skills to tackle complex issues</li>\n<li>Participate in planning, architecture, and research</li>\n<li>Perform complex development activities, including user experience, software design, and solver research</li>\n<li>Employ best practices and help maintain them through technical reviews and mentoring</li>\n<li>Perform complex bug verification, release testing, and beta support for assigned products</li>\n<li>Research problems discovered by QA or product support and develop solutions</li>\n<li>Research and understand marketing requirements for a product</li>\n<li>Work independently with minimal supervision and may take on some planning and mentoring responsibilities</li>\n</ul>\n<p>Minimum Qualifications:</p>\n<ul>\n<li>PhD or foreign equivalent in Mathematics, Computer Science, Computer Engineering, Mechanical Engineering, or a related field of study</li>\n<li>Alternatively, Master&#39;s degree or foreign equivalent in Mathematics, Computer Science, Computer Engineering, Mechanical Engineering, or a related field of study, and three years of experience in a related position</li>\n<li>Alternatively, Bachelor&#39;s degree or foreign equivalent in Mathematics, Computer Science, Computer Engineering, Mechanical Engineering, or a related field of study, and five years of experience in a related position</li>\n<li>Experience with development of iterative solvers and preconditioners for sparse linear systems</li>\n<li>Experience with high-performance computing methods, including distributed memory and shared memory parallel programming, with GPU programming in C, C++, and Fortran</li>\n<li>Experience using commercial and open-source linear algebra packages to implement numerical simulation workflows for computer-aided engineering</li>\n<li>Knowledge of error estimation for adaptive linear solvers in finite element, finite volume, and finite difference methods</li>\n<li>Knowledge of matrix approximation techniques like low-rank approximation, deflation, and randomized decomposition</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away, including company holidays, ETO, and FTO programs</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance</li>\n<li>ESPP, allowing purchase of Synopsys common stock at a 15% discount</li>\n<li>Retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>","enriched_at":1785792784159},{"id":"job_ca2199b3-f33","title":"Senior R&D Engineer","source_url":"https://careers.synopsys.com/job/canonsburg/senior-r-and-d-engineer/44408/98682479744","location":"Canonsburg, Pennsylvania","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>We are seeking a Senior R&amp;D Engineer to work in Canonsburg, PA, and various unanticipated locations. As a Senior R&amp;D Engineer at Synopsys, you will improve and enhance our Non-Linear solution procedure, Non-linear transient dynamics, and contact mechanics algorithms. You will perform R&amp;D in GPU acceleration for nonlinear finite element analysis procedure including contact modeling. Your responsibilities will also include:</p>\n<ul>\n<li>Working on performance improvement and memory reduction under HPC environments</li>\n<li>Designing, coding, testing, documenting, implementing, and maintaining software components and systems</li>\n<li>Contributing to and learning various aspects of the full software stack, including API design, database implementation, and parallel programming</li>\n<li>Performing moderately complex bug verification, release testing, and beta support</li>\n<li>Investigating problems discovered by QA or product support and developing solutions</li>\n<li>Participating in planning, architecture, and research</li>\n</ul>\n<p>To qualify, you will need:</p>\n<ul>\n<li>PhD or foreign equivalent in Mechanical, Structural, Civil Engineering, Computer Science, or a related field of study, and one (1) year of experience in a related position</li>\n<li>Or Master&#39;s degree or foreign equivalent in Mechanical, Structural, Civil Engineering, Computer Science, or a related field of study, and three (3) years of experience in a related position</li>\n<li>Or Bachelor&#39;s degree or foreign equivalent in Mechanical, Structural, Civil Engineering, Computer Science, or a related field of study, and five (5) years of experience in a related position</li>\n<li>Experience with contact mechanics, transient dynamics, and finite element coding experience</li>\n<li>Experience delivering high-quality products in a large-scale commercial software development environment</li>\n<li>Knowledge and commercial experience with object-oriented design, scripting languages, data structures, and algorithms</li>\n<li>Experience with Python, C/C++, and Fortran</li>\n</ul>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.</p>","enriched_at":1785792657514},{"id":"job_6119a0e4-50e","title":"Senior Technical Support Engineer – Structural Simulation / FEA","source_url":"https://careers.synopsys.com/job/pennsylvania/senior-technical-support-engineer-structural-simulation-fea/44408/98706276752","location":null,"job_type":"full-time","experience_level":"senior","work_arrangement":"remote","category":"Engineering","description":"<p>You are a technically strong engineer with a solid foundation in structural mechanics and simulation. Your role as a Senior Technical Support Engineer – Structural Simulation / FEA at Synopsys involves providing technical support to customers using Workbench Mechanical and LS-DYNA, troubleshooting complex simulation issues including model setup errors, solver failures, and unrealistic results.</p>\n<h4>Responsibilities</h4>\n<ul>\n<li>Provide technical support to customers using Workbench Mechanical and LS-DYNA, troubleshooting complex simulation issues including model setup errors, solver failures, and realistic results</li>\n<li>Review customer inputs, identify root causes, and recommend practical solutions for structural analysis, nonlinear mechanics, explicit dynamics, and multi-physics scenarios like crash and impact simulations</li>\n<li>Work directly with customers through email and virtual meetings to guide them on best practices and modeling approaches</li>\n<li>Investigate and reproduce reported issues, document findings, and collaborate with development teams on bug fixes and enhancements</li>\n<li>Build expertise in key application areas such as explicit dynamics, crash simulation, and NVH</li>\n<li>Support technical discussions, demos, and customer engagements alongside sales and application teams</li>\n<li>Develop and maintain technical content including knowledge base articles, workflow guides, and best practices that help customers and internal teams</li>\n</ul>\n<h4>The Impact You Will Have</h4>\n<ul>\n<li>Help customers solve complex engineering problems and successfully deliver critical simulation projects that directly affect their product development timelines</li>\n<li>Improve customer satisfaction by turning technical challenges into successful outcomes, reducing frustration and building long-term trust</li>\n<li>Accelerate simulation workflows and reduce costly design iterations through effective troubleshooting that gets customers unstuck faster</li>\n<li>Influence product development by providing real-world feedback to engineering teams about what works, what breaks, and what customers actually need</li>\n<li>Enable customers to adopt advanced simulation tools and workflows with confidence, expanding their capability and reliance on Synopsys solutions</li>\n<li>Strengthen Synopsys&#39; reputation as a trusted partner in engineering simulation through consistent, high-quality technical support</li>\n<li>Enhance internal knowledge and capability through collaboration and best practice sharing that lifts the entire team</li>\n</ul>\n<h4>Requirements</h4>\n<ul>\n<li>Bachelor&#39;s degree or higher in Mechanical Engineering, Civil Engineering, Aerospace Engineering, or a related field</li>\n<li>Strong fundamentals in structural mechanics, finite element analysis, and nonlinear simulation</li>\n<li>Experience with simulation tools such as LS-DYNA, Ansys, Abaqus, Nastran, Radioss, or OptiStruct</li>\n<li>Ability to troubleshoot and debug complex simulation problems, not just run models but understand when results don&#39;t add up</li>\n<li>Strong analytical and problem-solving skills that let you work through ambiguous or incomplete information</li>\n<li>Ability to clearly communicate technical concepts to both technical and non-technical audiences</li>\n<li>Experience in explicit dynamics or crash simulation is a plus, as is a Master&#39;s or PhD in a related field</li>\n</ul>\n<h4>Who You Are</h4>\n<ul>\n<li>You are comfortable working in a customer-facing role, managing multiple priorities and support cases without losing track of what matters most</li>\n<li>You take ownership of problems and drive them through to resolution, even when the path forward isn&#39;t immediately clear</li>\n<li>You can explain complex simulation and physics concepts clearly and effectively, adjusting your communication style based on who you&#39;re talking to</li>\n<li>You are methodical in your approach, focusing on root cause analysis and practical solutions rather than quick fixes that don&#39;t hold up</li>\n<li>You collaborate well across teams and contribute to a strong team culture, sharing what you learn and helping others grow</li>\n<li>You are motivated to grow your expertise and take on increasingly complex challenges, seeing each tough case as an opportunity to get better</li>\n</ul>\n<h4>The Team You&#39;ll Be Part Of</h4>\n<p>You will join the Ansys Customer Excellence (ACE) Global Technical Support (GTS) team, a globally distributed group of engineers dedicated to helping customers succeed with advanced simulation tools. The team works closely with customers and product development to solve complex challenges in structural mechanics and multi-physics analysis. With a strong focus on collaboration, knowledge sharing, and continuous learning, the team plays a key role in delivering customer success and driving product innovation.</p>\n<h4>Rewards and Benefits</h4>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>","enriched_at":1785792476466},{"id":"job_a1d323fb-646","title":"Staff Project Engineering Manager","source_url":"https://careers.synopsys.com/job/noida/staff-project-engineering-manager/44408/98689551632","location":"Noida, Uttar Pradesh","job_type":"full-time","experience_level":"staff","work_arrangement":null,"category":"Engineering","description":"<p>You will lead SerDes PHY IP projects that power the next generation of high-speed connectivity in everything from data centers to automotive systems.</p>\n<h4>Responsibilities</h4>\n<ul>\n<li>Manage end-to-end delivery of high-speed SerDes PHY IP projects from definition through tapeout and customer deployment</li>\n<li>Lead cross-functional project teams including design engineers, verification engineers, and layout specialists to execute against aggressive schedules</li>\n<li>Partner with R&amp;D and Marketing to define project roadmaps, prioritize features, and align technical deliverables with market requirements</li>\n<li>Identify resource gaps, manage project risks, and resolve cross-team dependencies before they block progress</li>\n<li>Drive process improvements across the engineering organization, implementing best practices that reduce cycle time and improve quality</li>\n<li>Collaborate with Sales, Marketing, and Customer Support teams on pre-sales technical engagement and post-sales issue resolution</li>\n<li>Deliver regular status updates to executive leadership and customers, translating technical progress into business outcomes</li>\n</ul>\n<h4>The Impact You Will Have</h4>\n<ul>\n<li>Accelerate time-to-market for advanced SerDes IP that enables high-speed connectivity in AI, automotive, and data center applications</li>\n<li>Enable customers to meet increasingly complex design requirements with proven, high-quality IP that integrates cleanly into their SoCs</li>\n<li>Strengthen Synopsys&#39; reputation as a trusted partner for mission-critical semiconductor IP through consistent on-time, on-spec delivery</li>\n<li>Improve engineering efficiency across the organization by identifying bottlenecks and implementing scalable processes that work across multiple projects</li>\n<li>Foster tighter collaboration between R&amp;D, Marketing, Sales, and Customer Support, ensuring alignment from early concept through customer deployment</li>\n<li>Contribute directly to Synopsys&#39; leadership position in high-speed interface IP, supporting customers building the next generation of smart, connected devices</li>\n<li>Mentor project leads and engineers on your team, building organizational capability in technical program management and cross-functional leadership</li>\n</ul>\n<h4>Requirements</h4>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of relevant experience, or Master&#39;s/PhD with 6+ years</li>\n<li>Deep technical knowledge of IC design, ASIC development flows, and semiconductor IP integration, particularly in mixed-signal or SerDes domains</li>\n<li>Proven track record leading complex engineering projects in a high-tech environment, ideally in semiconductor IP or ASIC development</li>\n<li>Strong risk management and change management skills, with experience navigating technical uncertainty and scope changes without derailing schedules</li>\n<li>Excellent stakeholder management and communication skills, you can explain technical tradeoffs to executives and translate customer requirements into actionable engineering plans</li>\n<li>Experience with SerDes PHY IP, high-speed interface standards like PCIe, USB, or Ethernet is a strong plus</li>\n<li>Familiarity with project management methodologies and tools, whether Agile, Waterfall, or hybrid approaches tailored to hardware development</li>\n</ul>","enriched_at":1785792417555},{"id":"job_5dca707d-853","title":"Applications Engineering, Staff Engineer","source_url":"https://careers.synopsys.com/job/porto-salvo/applications-engineering-staff-engineer/44408/93120696128","location":"Porto Salvo, Lisbon District","job_type":"full-time","experience_level":"staff","work_arrangement":null,"category":"Engineering","description":"<p>You are the person others call when the silicon refuses to cooperate and the test bench isn&#39;t telling the whole story. Your hands have been on oscilloscopes, spectrum analyzers, and BERTs more hours than you can count, and you know how to coax meaningful data out of noise.</p>\n<p>At Synopsys, you&#39;ll be at the center of the action, resolving the issues that keep products moving forward.</p>\n<h3>Responsibilities</h3>\n<ul>\n<li>Provide direct technical support to customers during silicon bring-up and production phases for high-speed SerDes IP</li>\n<li>Diagnose, troubleshoot, and resolve complex interoperability and performance issues involving analog and digital design layers</li>\n<li>Collaborate closely with internal analog, digital, and software teams to drive root cause analysis and implement solutions</li>\n<li>Use lab instrumentation including oscilloscopes, spectrum analyzers, BERTs, and network analyzers to perform hands-on debug and precision measurements</li>\n<li>Interpret and simulate Verilog/RTL to understand and isolate digital design issues impacting silicon behavior</li>\n<li>Analyze protocol-specific behaviors for PCIe and Ethernet during link training and operation to identify and resolve failures</li>\n<li>Document findings and best practices, communicating technical insights clearly to both customers and internal teams</li>\n</ul>\n<h3>The Impact You Will Have</h3>\n<ul>\n<li>Accelerate customer silicon bring-up cycles by resolving blockers that could delay product launches</li>\n<li>Increase the reliability and performance of deployed SerDes IP by surfacing and addressing subtle system-level issues</li>\n<li>Enable customers to achieve first-pass silicon success, reducing costly re-spins and engineering churn</li>\n<li>Improve internal R&amp;D processes by feeding real-world debug insights back into design and validation teams</li>\n<li>Foster trust and credibility with key customers through technical leadership and responsive support</li>\n<li>Raise the technical bar within the team by sharing advanced debug techniques and test methodologies</li>\n</ul>\n<h3>Requirements</h3>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s in Electrical or Electronic Engineering or similar education with at least 5+ years of experience</li>\n<li>Solid experience with electronics test and debug instrumentation including oscilloscopes, spectrum analyzers, BERTs, and network analyzers</li>\n<li>Strong understanding of high-speed SerDes applications, including analog and digital design interactions</li>\n<li>Familiarity with PCIe and Ethernet protocols, especially the link training phases and common failure modes</li>\n<li>Experience interpreting and simulating Verilog/RTL for debug purposes is highly valuable</li>\n<li>Practical knowledge of IC design and high-speed board/system bring-up is a plus</li>\n<li>Experience executing precision measurements and troubleshooting at the silicon and system level</li>\n</ul>\n<h3>Who You Are</h3>\n<ul>\n<li>You see a failing test as a puzzle to solve, not a setback, and you keep digging until you find the root cause</li>\n<li>You communicate technical findings clearly, whether you&#39;re writing up a debug summary or walking a customer through a scope trace</li>\n<li>You are comfortable switching gears between lab work, code analysis, and cross-team meetings, prioritizing what moves the needle</li>\n<li>You naturally build bridges between analog, digital, and software teams, making sure details don&#39;t fall through the cracks</li>\n<li>You manage your time and workload with little direction, always keeping the bigger picture in view</li>\n<li>You document your process so others can learn from your discoveries and avoid the same pitfalls</li>\n</ul>\n<h3>The Team You&#39;ll Be Part Of</h3>\n<p>Join a dynamic, highly skilled multi-sites team of Applications Engineers and IPs integration specialists at Synopsys. The team partners closely with customers across the globe, providing technical expertise and integration support for industry-leading Interface IP. Collaboration, knowledge sharing, and a passion for innovation are at the core of our team culture. Together, we enable our customers to deliver breakthrough semiconductor solutions that set new benchmarks for performance and reliability.</p>\n<h3>Rewards and Benefits</h3>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>","enriched_at":1785792369622},{"id":"job_b1f85c2b-555","title":"R&D Engineer II","source_url":"https://careers.synopsys.com/job/waltham/r-and-d-engineer-ii/44408/98682479792","location":"Waltham, Massachusetts","job_type":"full-time","experience_level":"mid","work_arrangement":null,"category":"Engineering","description":"<p>We are seeking an R&amp;D Engineer II to work in Waltham, MA. As an R&amp;D Engineer II, you will contribute to the development of software products and supporting systems. You will collaborate with a team of expert professionals to understand customer requirements and accomplish development objectives.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Perform moderately complex development activities, including design, implementation, maintenance, testing, and documentation of software modules and sub-systems.</li>\n<li>Perform moderately complex bug verification, release testing, and beta support for assigned products.</li>\n<li>Research problems discovered by QA or product support and develop solutions.</li>\n<li>Understand marketing requirements for a product, including target environment, performance criteria, and competitive issues.</li>\n</ul>\n<p>Minimum Qualifications:</p>\n<ul>\n<li>Master&#39;s degree or foreign equivalent in Computer Science, Software Engineering, or a related field of study.</li>\n<li>Alternatively, a Bachelor&#39;s degree or foreign equivalent in Computer Science, Software Engineering, or a related field of study, and two years of experience in a related position.</li>\n<li>Experience designing and implementing RESTful APIs.</li>\n<li>Experience with relational and NoSQL databases for storing and querying application data.</li>\n<li>Experience working with AWS, particularly with serverless functions, S3, SQS, and CloudWatch.</li>\n<li>Experience working with Docker to build and containerize cloud-native applications in a large-scale software development environment.</li>\n</ul>\n<p>Rate of Pay: $131,082.00 per year.</p>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans.</li>\n<li>Time away programs, including ETO and FTO.</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.</li>\n<li>ESPP program.</li>\n<li>Retirement plans.</li>\n</ul>","enriched_at":1785792329521},{"id":"job_2c84e2cf-786","title":"Senior Application Engineer","source_url":"https://careers.synopsys.com/job/waltham/senior-application-engineer/44408/98682479840","location":"Waltham, MA","job_type":"full-time","experience_level":"senior","work_arrangement":"hybrid","category":"Engineering","description":"<p>We are seeking a Senior Application Engineer to work in Waltham, MA. As a Senior Application Engineer, you will lead in coordinating and executing all technical activities throughout the sales opportunity lifecycle.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Lead technical discovery, negotiation of technical success criteria, product presentations, demonstrations, and evaluations</li>\n<li>Work independently within multi-disciplinary teams and interact with customers to understand their product design needs and engineering design workflows</li>\n<li>Analyze how to address customers&#39; requirements using Ansys products and platform, articulate Ansys&#39; value proposition</li>\n<li>Assist in creating differentiating simulation solutions using the Ansys platform and products; deploy the solutions within customers&#39; design workflows</li>\n<li>Develop competence as a subject matter expert and industry expert</li>\n<li>Collaborate with the Ansys product development teams to translate customer requirements into exciting new product features; test new releases of Ansys products on industrial problems, develop application best practices</li>\n<li>Support Ansys field and digital marketing, author conference presentations</li>\n<li>Contribute to consulting services, conduct introductory and/or intermediate training classes</li>\n</ul>\n<p>Minimum Qualifications:</p>\n<ul>\n<li>Master&#39;s degree or foreign equivalent in Mechanical, Chemical, Aerospace, Electrical Engineering, Physics or a related field of study, and three (3) years of experience in a related position</li>\n<li>Alternate Acceptable Education and Work Experience Requirement: Bachelor&#39;s degree or foreign equivalent in Mechanical, Chemical, Aerospace, Electrical Engineering, Physics or a related field of study, and five (5) years of experience in a related position</li>\n<li>Knowledge and previous usage of Ansys HFSS, Ansys SIwave, Ansys Q3D Extractor or other commercial simulation software involving real-world, industry-level electromagnetics applications</li>\n<li>Knowledge of RF circuit packaging, printed circuit boards and connector design processes and simulations</li>\n<li>Knowledge of antenna, phased array, radar cross-section, antenna installation and co-site analyses and communication channel characterization</li>\n<li>Knowledge of high-frequency electromagnetics, microwave and antenna concepts including S-parameters, wave propagation, antenna radiation patterns, scattering analysis, and component coupling/interference analysis</li>\n<li>Ability to travel domestically up to 25% of the time</li>\n<li>May permit telecommuting from home office within commuting distance to Waltham, MA office</li>\n</ul>\n<p>Rate of Pay: $167,627.00 per year</p>","enriched_at":1785792030600},{"id":"job_7a2e9e69-86a","title":"Senior System Architecture Specialist","source_url":"https://careers.synopsys.com/job/moreira/senior-system-architecture-specialist/44408/98706276736","location":"Moreira, Porto","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>You are a UCIe / Die-to-Die System Architecture Specialist who can work directly with customer architects to close real system-level chiplet and multi-die design decisions.</p>\n<p>You will help customers integrate die-to-die IPs into complex ASIC, SoC, and multi-die platforms, identify key requirements or gaps, and translate customer feedback into actionable input for Synopsys Product Management, R&amp;D, and roadmap planning.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Own the technical architecture engagement for UCIe / die-to-die IP with strategic customers, from early chiplet and multi-die platform requirements through architecture closure and initial deployment readiness.</li>\n<li>Work with customer architects and engineering teams to define suitable UCIe/ die-to-die subsystem configurations for advanced ASIC, SoC, and multi-die platforms.</li>\n<li>Analyze system-level trade-offs related to protocol selection, bandwidth, latency, power, area, packaging considerations, validation, compliance, and interoperability.</li>\n<li>Translate customer platform requirements, integration constraints, and deployment feedback into clear input for Synopsys Product Management, R&amp;D, and roadmap planning.</li>\n<li>Support technical closure of design wins by providing architecture guidance, configuration recommendations, risk assessment, and competitive positioning.</li>\n<li>Develop reusable technical material, application notes, and customer-facing guidance based on real engagement experience.</li>\n<li>Train FAEs and customer teams on UCIe architecture, die-to-die integration trade-offs, validation expectations, and deployment best practices.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Improve the quality of UCIe / die-to-die design wins by ensuring customer chiplet and multi-die architectures are technically sound before commitment.</li>\n<li>Strengthen the Synopsys UCIe roadmap by feeding real customer system, packaging, protocol, and integration requirements into product planning and R&amp;D execution.</li>\n<li>Reduce customer integration risk by identifying architecture, configuration, validation, interoperability, and implementation issues early.</li>\n<li>Help establish Synopsys as a trusted technical partner for next-generation AI, HPC, automotive, networking, and chiplet-based platforms.</li>\n<li>Provide technical training to FAEs and key customers on UCIe architecture, die-to-die IP products, integration trade-offs, and deployment best practices.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor’s and/or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or Computer Science.</li>\n<li>5+ years of experience in semiconductor IP, SoC architecture, systems engineering, applications engineering, silicon validation, or customer-facing technical roles.</li>\n<li>Solid understanding of UCIe / die-to-die IP concepts and system integration considerations.</li>\n<li>Good system-level understanding of ASIC, SoC, and multi-die integration, with the ability to evaluate key performance and implementation trade-offs.</li>\n<li>Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers.</li>\n<li>Ability to translate ambiguous customer requirements into clear technical recommendations, product feedback, and closure plans.</li>\n<li>Strong technical communication skills, including clear written analysis, structured trade-off explanation, and ability to align customer, sales, product, and engineering teams.</li>\n</ul>\n<p>Nice to Have:</p>\n<ul>\n<li>Familiarity with one or more protocols commonly used in chiplet and die-to-die systems, such as AXI, PCIe, CXL, CHI-C2C, CXS, or Streaming.</li>\n<li>Familiarity with multi-die architectures, advanced packaging technologies, and associated integration trade-offs.</li>\n<li>Prior experience selecting, using, designing, or supporting internal or external IP.</li>\n<li>Prior experience in application engineering or another direct customer-facing role.</li>\n<li>Familiarity with implementation or validation flows, including RTL design, verification, synthesis, static timing analysis, simulation, or silicon bring-up.</li>\n</ul>\n<p>Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>","enriched_at":1785791618303}],"category_normalised":[{"category":"engineering","count":248},{"category":"finance","count":6},{"category":"it","count":6},{"category":"sales","count":4},{"category":"operations","count":3},{"category":"marketing","count":2},{"category":"legal","count":2},{"category":"manufacturing","count":1},{"category":"hr","count":1}],"velocity":{"weeks":[{"week_start":"2026-02-02","count":1},{"week_start":"2026-02-09","count":1},{"week_start":"2026-03-02","count":20},{"week_start":"2026-03-30","count":10},{"week_start":"2026-04-20","count":22},{"week_start":"2026-04-27","count":6},{"week_start":"2026-05-04","count":11},{"week_start":"2026-05-11","count":8},{"week_start":"2026-05-18","count":15},{"week_start":"2026-05-25","count":24},{"week_start":"2026-06-01","count":19},{"week_start":"2026-06-08","count":17},{"week_start":"2026-06-15","count":12},{"week_start":"2026-06-22","count":7},{"week_start":"2026-06-29","count":18},{"week_start":"2026-07-06","count":12},{"week_start":"2026-07-13","count":21},{"week_start":"2026-07-20","count":18},{"week_start":"2026-07-27","count":22},{"week_start":"2026-08-03","count":2}],"trend":"accelerating","wow_pct":-91},"momentum":{"recent_14d":37,"prior_14d":32,"growth_pct":16,"classification":"accelerating"},"salary_vs_industry":{"company_median":198500,"industry_median":214508,"percentile":34,"sample_size":69,"by_region":[{"region":"United States","company_median":210500,"industry_median":null,"sample":42},{"region":"Unknown","company_median":172500,"industry_median":null,"sample":27}],"transparency_pct":25,"industry_transparency_pct":33,"transparency_warning":false},"market_share":{"company_jobs":275,"industry_total":1042,"share_pct":26.4,"rank":2,"peer_count":2},"ai_exposure":{"occupation_weighted_score":0.159,"skill_weighted_score":0.291,"top_exposed_titles":[{"title":"R&D Engineering, Staff Engineer","count":7,"score":0.145},{"title":"Applications Engineering, Staff Engineer","count":7,"score":0.145},{"title":"Applications Engineering, Sr Staff Engineer","count":4,"score":0.145},{"title":"Analog Design, Sr Staff Engineer","count":4,"score":0.145},{"title":"Principal SerDes Systems Engineer","count":3,"score":0.276},{"title":"ASIC Digital Design, Sr Staff Engineer","count":3,"score":0.145},{"title":"ASIC Digital Design, Principal Engineer","count":3,"score":0.145},{"title":"Staff Software Engineer","count":2,"score":0.288},{"title":"Staff Application Engineer – Physical Implementation","count":2,"score":0.081},{"title":"Senior Staff RTL Design Engineer","count":2,"score":0.075}],"top_exposed_skills":[{"skill":"Python Scripting","count":3,"score":0.389},{"skill":"Git","count":3,"score":0.35},{"skill":"Device Physics","count":3,"score":0.32},{"skill":"Artificial Intelligence","count":3,"score":0.309},{"skill":"EDA","count":4,"score":0.276},{"skill":"Semiconductor","count":4,"score":0.276},{"skill":"English","count":3,"score":0.272},{"skill":"Product Management","count":6,"score":0.266},{"skill":"Ansys HFSS","count":3,"score":0.249},{"skill":"UNIX/Linux","count":3,"score":0.24}]},"peer_set":[{"slug":"databricks","name":"Databricks","total_jobs":767,"similarity":0.67,"momentum_classification":"stable"}],"skills_lq":[{"skill":"Scripting Languages","company_count":9,"company_pct":3.3,"industry_pct":0.1,"lq":25.1,"required_pct":100},{"skill":"Software Development","company_count":6,"company_pct":2.2,"industry_pct":0.1,"lq":16.73,"required_pct":100},{"skill":"Shell Scripting","company_count":6,"company_pct":2.2,"industry_pct":0.1,"lq":16.73,"required_pct":83},{"skill":"Linux","company_count":8,"company_pct":2.9,"industry_pct":0.3,"lq":11.16,"required_pct":100},{"skill":"REST APIs","company_count":3,"company_pct":1.1,"industry_pct":0.1,"lq":8.37,"required_pct":100},{"skill":"Business Development","company_count":3,"company_pct":1.1,"industry_pct":0.1,"lq":8.37,"required_pct":67},{"skill":"Git","company_count":3,"company_pct":1.1,"industry_pct":0.1,"lq":8.37,"required_pct":67},{"skill":"Anaplan","company_count":3,"company_pct":1.1,"industry_pct":0.3,"lq":4.18,"required_pct":100},{"skill":"Scripting","company_count":5,"company_pct":1.8,"industry_pct":0.5,"lq":3.49,"required_pct":100},{"skill":"Debugging","company_count":5,"company_pct":1.8,"industry_pct":0.7,"lq":2.79,"required_pct":80},{"skill":"Data Visualization","company_count":3,"company_pct":1.1,"industry_pct":0.5,"lq":2.09,"required_pct":33},{"skill":"Business Intelligence","company_count":3,"company_pct":1.1,"industry_pct":0.5,"lq":2.09,"required_pct":67},{"skill":"Snowflake","company_count":3,"company_pct":1.1,"industry_pct":0.5,"lq":2.09,"required_pct":100},{"skill":"Ci/cd Pipelines","company_count":3,"company_pct":1.1,"industry_pct":0.7,"lq":1.67,"required_pct":67},{"skill":"Analytical Skills","company_count":3,"company_pct":1.1,"industry_pct":0.7,"lq":1.67,"required_pct":100},{"skill":"AI Tools","company_count":3,"company_pct":1.1,"industry_pct":0.7,"lq":1.67,"required_pct":100},{"skill":"English","company_count":4,"company_pct":1.5,"industry_pct":0.9,"lq":1.59,"required_pct":100},{"skill":"Communication Skills","company_count":8,"company_pct":2.9,"industry_pct":2,"lq":1.49,"required_pct":88},{"skill":"C#","company_count":4,"company_pct":1.5,"industry_pct":1,"lq":1.39,"required_pct":100},{"skill":"APIs","company_count":4,"company_pct":1.5,"industry_pct":1,"lq":1.39,"required_pct":75}],"geographic_shift":{"current":[{"region":"India","count":80,"share_pct":31.4},{"region":"Unknown","count":73,"share_pct":28.6},{"region":"United States","count":50,"share_pct":19.6},{"region":"APAC","count":27,"share_pct":10.6},{"region":"EU","count":17,"share_pct":6.7},{"region":"Canada","count":5,"share_pct":2},{"region":"Africa","count":2,"share_pct":0.8},{"region":"United Kingdom","count":1,"share_pct":0.4}],"emerging":[{"region":"Unknown","recent_30d":18,"prior_30d":10,"growth_pct":80},{"region":"United States","recent_30d":16,"prior_30d":8,"growth_pct":100}],"shrinking":[{"region":"EU","recent_30d":3,"prior_30d":5,"growth_pct":-40}]},"seniority_anomalies":{"exec_recent_30d":8,"exec_prior_90d_avg":4.3,"exec_growth_pct":86,"notable_exec_hires":[{"title":"People Partner, Sr Director","location":"Exton, Pennsylvania","posted_at":"2026-07-28"},{"title":"Financial Planning & Analysis, Sr Director","location":"Exton, Pennsylvania","posted_at":"2026-07-28"},{"title":"Senior Director R&D Engineering (Interface PHY / Ethernet SerDes)","location":"Ottawa, Ontario","posted_at":"2026-07-25"},{"title":"Foundry Product Marketing, Director","location":"Taipei","posted_at":"2026-07-21"},{"title":"Director of Data Engineering & Analytics","location":null,"posted_at":"2026-07-16"}]},"posting_dynamics":{"median_days_open":61,"industry_median_days_open":43,"long_open_count":74,"closure_rate_pct":72}}}}