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CA","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>We&#39;re building the next generation of compiler technologies to accelerate deep learning workloads. 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The expected base salary range for this position is 116,000 USD – 189,750 USD. You will also be eligible for equity and benefits.</p>","enriched_at":1793587228575},{"id":"job_fa699e5d-018","title":"Senior Service Delivery Manager","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Singapore-Singapore-Suntec-Tower/Senior-Project-Delivery-Manager--NVIS_JR2026777-1","location":"Singapore","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>We are seeking a Senior Service Delivery Manager to lead end-to-end project delivery for enterprise data center environments. You will own the full project lifecycle from strategic alignment and solution design through deployment, stabilization, and production handover.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Build and maintain trusted, long-term working relationships with customers, internal stakeholders, and partner teams.</li>\n<li>Understand high-level and detailed technical architectures, facilitate technical discussions, and drive decision-making for optimal solution design.</li>\n<li>Ensure project requirements, deliverables, and documentation adhere to NVIDIA quality standards and are completed on schedule.</li>\n<li>Develop, present, and defend comprehensive technical solutions and deployment plans to executive and technical customer audiences.</li>\n<li>Lead regular syncs, governance calls, and status updates with global internal teams, customers, and third-party partners.</li>\n<li>Own delivery of complex on-site or remote data center installations, escalate issues appropriately, and drive resolution with cross-functional partners.</li>\n<li>Manage project change requests, release communications, and customer notifications in a clear and timely manner.</li>\n<li>Create clear, concise technical and operational runbooks, procedures, and post-implementation documentation.</li>\n<li>Demonstrate flexibility to support on-call, off-hours, or global time zone requirements as needed for critical deployments.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Engineering, Computer Science, or a related technical field (or equivalent professional experience).</li>\n<li>5+ years of progressive experience in project delivery management or customer service delivery leadership.</li>\n<li>5+ years of field service, customer implementation, or post-sales support experience for enterprise hardware &amp; software platforms.</li>\n<li>Deep working knowledge of data center infrastructure: servers, storage, networking, cabling, power, cooling, and physical deployment workflows.</li>\n<li>Strong customer-facing interpersonal skills and ability to engage directly with C-level and technical stakeholders.</li>\n<li>Proven leadership experience across cross-functional, global, and diverse teams.</li>\n<li>Excellent verbal, written, and presentation communication skills.</li>\n<li>Strong organizational skills, ability to prioritize effectively, and manage multiple complex projects with minimal supervision.</li>\n<li>Experience leading global projects across regions and time zones.</li>\n</ul>\n<p><strong>Preferred Qualifications:</strong></p>\n<ul>\n<li>PMP or equivalent project management certification.</li>\n<li>Hands-on experience with HPC clusters, InfiniBand, GPU infrastructure, or hyperscale data center technologies.</li>\n<li>Experience in AI infrastructure deployment, professional services, or tech vendor post-sales delivery.</li>\n</ul>","enriched_at":1793448725805},{"id":"job_49e0be32-27e","title":"Senior Package Layout Engineer","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Package-Layout-Engineer---Hardware_JR2028970","location":"Bengaluru, India","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>NVIDIA is seeking a Senior Package Layout Engineer to join their team in Bengaluru, India. The successful candidate will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Collaborate with the Layout team to implement high-speed/density ASIC packages</li>\n<li>Perform substrate breakout patterns for ASIC packages</li>\n<li>Optimize package pinout incorporating system-level trade-offs of pins assignment</li>\n<li>Help perform package routing, placement, stack-up, reference plane, and power distribution using Cadence APD or SiP tool suite</li>\n<li>Propose layout design trade-offs to the Technical Package Lead for resolution and implementation</li>\n<li>Conduct design feasibility studies to evaluate Package design goals for size, cost, and system performance</li>\n<li>Develop symbols and CAD library databases using Cadence APD design tools</li>\n<li>Develop methodologies to improve layout productivity</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Hold a B.S. in Electrical Engineering or equivalent experience</li>\n<li>3+ years of experience in PCB Layout of graphics cards, motherboards, line cards, or other related technology</li>\n<li>Proven experience in substrate layout of wire bond and flip chip packages is preferred</li>\n<li>Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager)</li>\n<li>Solid understanding of high-speed design signal integrity practices</li>\n<li>Experience with Virtuoso and Calibre is a plus</li>\n<li>Experience using Valor is helpful</li>\n</ul>","enriched_at":1793448712275},{"id":"job_00303c14-cce","title":"Senior System Software Engineer","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Hyderabad/Senior-System-Software-Engineer---GPU_JR2028568","location":null,"job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>NVIDIA is seeking an outstanding Senior System Software Engineer to join our Display Driver team. You will develop production-quality system software for next-generation NVIDIA GPU and Tegra platforms, working across operating systems such as Linux and Android.</p>\n<p>The role combines broad kernel-mode driver development with opportunities to work on display security technologies, including High-bandwidth Digital Content Protection (HDCP). You will collaborate with hardware, firmware, security, and system software teams to deliver reliable and secure display solutions.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Design, develop, test, and maintain GPU/display kernel-mode drivers and embedded firmware.</li>\n<li>Develop system software across Linux, Android or similar operating system.</li>\n<li>Implement and maintain HDCP and related display-content-protection functionality.</li>\n<li>Debug interactions across software, firmware, hardware, and external display devices.</li>\n<li>Develop multithreaded, performance-sensitive software in C.</li>\n<li>Participate in design, code, and security reviews.</li>\n<li>Build automated tests and diagnostic tools to improve reliability and interoperability.</li>\n<li>Collaborate with teams across NVIDIA and external partners throughout the product lifecycle.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS or MS in Computer Science, Electrical Engineering, Computer Engineering, or equivalent experience.</li>\n<li>5+ years of experience developing system software, embedded software, firmware, or kernel-mode drivers.</li>\n<li>Strong C programming and debugging skills.</li>\n<li>Solid understanding of operating-system fundamentals, computer architecture, memory management, synchronization, and concurrency.</li>\n<li>Experience developing low-level software on Linux, Android, or a similar operating system.</li>\n<li>Familiarity with secure protocols, cryptographic concepts, authentication, key management, or content-protection technologies.</li>\n<li>Strong analytical, communication, and collaboration skills.</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Experience implementing or debugging HDCP 1.x/2.x authentication and content-protection flows.</li>\n<li>Knowledge of HDMI, DisplayPort, USB-C DisplayPort Alt Mode, DDC/I²C, or DisplayPort AUX protocols.</li>\n<li>Experience with Linux DRM/KMS or graphics/display kernel drivers.</li>\n<li>Familiarity with trusted execution environments, secure firmware, hardware security modules, or secure key provisioning.</li>\n<li>Experience in debugging display interoperability, or content-protection certification issues.</li>\n</ul>","enriched_at":1793448701200},{"id":"job_48d3a979-739","title":"Senior Mask Layout Design Engineer","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mask-Design-Engineer---Hardware_JR1966157","location":"Santa Clara, CA","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>We are looking for a Senior Mask Layout Design Engineer to join a growing team responsible for handling high-speed mixed-signal circuit designs.</p>\n<p><strong>Job Summary:</strong> As a Senior Mask Layout Design Engineer, you will perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and Analog to Digital converters in state-of-the-art sub-micron CMOS technologies using Cadence tools. You will work cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Perform physical layout for mixed-signal functions using Cadence tools</li>\n<li>Work cross-functionally with ASIC and mixed-signal engineers to customize designs</li>\n<li>Take part in floor planning, custom layout, and verifying against design rules and schematics</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BSEE or equivalent experience</li>\n<li>Minimum of 7+ years of industry experience in Mask and Layout Design</li>\n<li>Deep understanding of analog circuit layout concepts in submicron CMOS technologies</li>\n<li>Expertise with Cadence custom circuit design tools, particularly Virtuoso</li>\n<li>Experience with verification tools such as Dracula, Hercules, Calibre, and Primeyield</li>\n<li>Proficiency in scripting languages like Perl, Python, and Skill</li>\n<li>Knowledge of DRC and LVS checking flows, ability to customize decks</li>\n</ul>\n<p><strong>Salary:</strong> The expected base salary ranges for this position are: 132,000 USD – 207,000 USD for Level 4; and 148,000 USD – 235,750 USD for Level 5.</p>\n<p><strong>Benefits:</strong> You will also be eligible for equity and benefits.</p>","enriched_at":1793448685265},{"id":"job_5b5f5e48-b19","title":"Deep Learning Compiler CI/CD Infrastructure Engineer","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shenzhen/Deep-Learning-Compiler-CI-Infrastructure-Engineer_JR2020326","location":"Shenzhen","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>In this role, you will work closely with deep learning compiler engineers to own and evolve the CI/CD infrastructure that powers the development lifecycle of NVIDIA&#39;s deep learning compiler stacks.</p>\n<p>Responsibilities include designing and operating scalable CI systems that orchestrate ML workloads across diverse GPU and accelerator environments, deliver reliable correctness and performance signals, and serve as a primary technical point of contact for CI health, new project onboarding, and new architecture bring-up.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Build, maintain, and improve CI infrastructure that supports development, verification, and release of NVIDIA’s deep learning compiler stacks across GPU and accelerator environments</li>\n<li>Improve CI reliability and signal quality by reducing flakes, improving reproducibility, strengthening diagnostics, and making correctness and performance failures easier to understand and act on</li>\n<li>Apply automation, AI, and agent-based workflows to reduce manual CI operations, speed up failure triage, and improve developer efficiency</li>\n<li>Build reusable and self-service CI platforms that support multiple products, projects, model suites, hardware targets, and software configurations while partnering closely with compiler, infrastructure, and release teams</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BS, MS, or PhD (or equivalent experience) in Computer Science, Computer/Electrical Engineering, Mathematics, or a related field</li>\n<li>5+ years of experience designing, scaling, and operating CI/CD, build/release, or developer infrastructure for complex software systems</li>\n<li>Proven experience building CI platforms end-to-end using systems such as GitLab CI, Jenkins, or similar tools, including pipeline orchestration, compute/runner management, artifact and package systems, and observability, with strong emphasis on reliability, reproducibility, and debuggability</li>\n<li>Strong software engineering skills (Python required), with the ability to design, implement, and debug distributed systems end-to-end</li>\n<li>Familiarity with edge devices (SOC, e.g. NVIDIA Tegra) in host-target architecture, ability to debug it and knowledge to its automation nuances</li>\n<li>Proven track record of designing, building, and deploying AI/LLM-based systems in real engineering workflows, demonstrating skill in evaluating trade-offs, failure modes, maintainability, and measurable impact on developer productivity, signal quality, or operational efficiency</li>\n</ul>\n<p><strong>Nice to Have:</strong></p>\n<ul>\n<li>Experience crafting and shipping sophisticated AI/agent-based systems that improve continuous integration or developer efficiency. These systems include intelligent test selection, automated triage and routing, regression localization, autonomous remediation, and developer-assist workflows</li>\n<li>Experience operating CI for DL/GPU software environments, including multi-GPU / multi-node workloads on Slurm, Kubernetes, or cloud platforms</li>\n<li>Familiarity with compiler IRs and infrastructure such as LLVM/MLIR, TensorRT IR, especially in the context of testing, debugging, and validating compiler-driven workloads</li>\n</ul>","enriched_at":1793448667049},{"id":"job_2b5e4fbd-df7","title":"Healthcare Life Science (HCLS) AI Startup Lead","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Singapore-Singapore-Suntec-Tower/Healthcare-AI-Startups-Lead---APAC_JR2028892","location":"Singapore","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Sales","description":"<p>We are seeking a passionate and driven Healthcare Life Science (HCLS) AI Startup Lead to build and scale NVIDIA&#39;s developer ecosystem across APAC. Today, over 5,000 healthcare life science startups participate in NVIDIA&#39;s Inception program and this region is critical in continuing to grow participation and engagement with HCLS startup community.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Engage the HCLS AI Startup Community in APAC region - Build and scale programs that connect regional HCLS startups to NVIDIA technologies, building from NVIDIA&#39;s Inception programs, regional hubs, accelerators, and events efficiently at scale.</li>\n<li>Engage regional Venture Capital firms and funding entities at scale - Extend NVIDIA programs to regional VCs and other HCLS AI investors, engaging them to scale and accelerate adoption of NVIDIA technology to startups.</li>\n<li>Drive Regional Strategy, Execution, and Operational Excellence - Develop and execute regional strategies; define and track operational metrics to continuously improve startup and VC engagement at scale.</li>\n<li>Act as Regional Interface and SME - Serve as NVIDIA&#39;s subject matter expert and main interface for the HCLS startup ecosystem in APAC, surfacing feedback and ensuring alignment with global teams.</li>\n<li>Ability to navigate fast-moving startup ecosystems, understands how to engage the HCLS startup community in the APAC region, including VCs and accelerators, and brings the creativity and intensity to lead teams, engage founders, and scale developer impact across the region.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>10 years + of experience in developing and delivering startup engagement programs at scale, developer relations, business development, or startup ecosystems</li>\n<li>Bachelors in a related degree of equivalent experience.</li>\n<li>Deep understanding of APAC HCLS startup and VC communities</li>\n<li>Track record of building and scaling developer or startup engagement programs</li>\n<li>Strong communication and program management skills</li>\n</ul>\n<p><strong>Nice to Have:</strong></p>\n<ul>\n<li>Knowledge of AI, machine learning, or HPC technologies</li>\n<li>Experience with regional VC, incubator hub, etc</li>\n<li>Familiarity with region&#39;s major startup hubs</li>\n</ul>\n<p>NVIDIA is at the forefront of AI and accelerated computing, widely regarded as one of the most innovative companies in technology. You will have the opportunity to:</p>\n<ul>\n<li>Work with ground breaking technology crafting the future of AI and startups</li>\n<li>Build communities and programs that empower thousands of developers</li>\n<li>Collaborate in a culture that values creativity, autonomy, and impact</li>\n</ul>","enriched_at":1793448633936},{"id":"job_49464380-acc","title":"Senior Engineer - Mixed-Signal Design","source_url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Mixed-Signal-Design-Engineer_JR1966431","location":"Santa Clara, CA","job_type":"full-time","experience_level":"senior","work_arrangement":null,"category":"Engineering","description":"<p>We are seeking a senior engineer to join our mixed-signal design team, responsible for building next-generation NVLINK technology. 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debugging</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Master&#39;s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with a strong analog design background</li>\n<li>2 years of analog design experience in industry</li>\n<li>Experience with CMOS analog/mixed-signal circuit design in deep sub-micron processes, especially FINFET</li>\n<li>Familiarity with design and verification tools like Cadence&#39;s IC design environment, Spectre, HSpice, and Finesim</li>\n<li>Experience in crafting test bench environments for component and top-level circuit verification</li>\n<li>Strong debugging and analytical skills</li>\n<li>Ability to work collaboratively as a team player</li>\n</ul>\n<p><strong>Benefits:</strong></p>\n<ul>\n<li>Competitive salary: $136,000 - $218,500 (Level 3) or $168,000 - $264,500 (Level 4)</li>\n<li>Equity and benefits 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